Heiko, On Sun, Nov 8, 2015 at 8:04 AM, Heiko Stuebner <heiko at sntech.de> wrote: > The otgphy clocks really only drive the phy blocks. These in turn > contain plls that then generate the 480m clocks the clock controller > uses to supply some other clocks like uart0, gpu or the video-codec. > > So fix this structure to actually respect that hirarchy and removed > that usb480m fixed-rate clock working as a placeholder till now, as > this wouldn't even work if the supplying phy gets turned off while > its pll-output gets used elsewhere. > > Signed-off-by: Heiko Stuebner <heiko at sntech.de> > --- > drivers/clk/rockchip/clk-rk3188.c | 11 +++-------- > drivers/clk/rockchip/clk-rk3288.c | 16 +++++----------- > 2 files changed, 8 insertions(+), 19 deletions(-) Reviewed-by: Douglas Anderson <dianders at chromium.org>
