On Mon, Nov 02, 2015 at 11:14:00AM +0800, Caesar Wang wrote: > In order to support more rates, add the divider clock api. > As the input source clock to the module is MCLK_I2S, > and by the divider of the module, the clock generator generates > SCLK and LRCK to transmitter and receiver. Why is this a requirement? The clock to use as a source should normally be specified via set_sysclk() and any internal dividers calculated automatically by the driver. -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 473 bytes Desc: not available URL: <http://lists.infradead.org/pipermail/linux-rockchip/attachments/20151104/4932e765/attachment.sig>
