Hi Mike,
here is a bunch of clock changes for 3.20.
As the tag message explains, some new clock ids, a flag, a dummy clock
and slowing down the plls on suspend, nothing to intrusive I hope.
So if it looks ok, please pull
Thanks
Heiko
The following changes since commit 97bf6af1f928216fd6c5a66e8a57bfa95a659672:
Linux 3.19-rc1 (2014-12-20 17:08:50 -0800)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git tags/v3.20-rockchip-clk1
for you to fetch changes up to e142a4e91443d0fc2185c821626e66729f323d1c:
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288 (2015-01-22 15:42:24 +0100)
----------------------------------------------------------------
The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.
Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.
----------------------------------------------------------------
Doug Anderson (2):
clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
Heiko Stuebner (3):
clk: rockchip: add id for watchdog pclk on rk3288
Merge branch 'v3.20-clk/new-ids' into v3.20-clk/next
clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
Huang Lin (1):
clk: rockchip: add clock IDs for the PVTM clocks
Kever Yang (2):
clk: rockchip: add clock ID for usbphy480m_src
clk: rockchip: use the clock ID for usbphy480m_src
huang lin (1):
clk: rockchip: add PVTM clocks on rk3288
drivers/clk/rockchip/clk-rk3288.c | 48 +++++++++++++++++++++++++---------
include/dt-bindings/clock/rk3288-cru.h | 4 +++
2 files changed, 39 insertions(+), 13 deletions(-)
