From: ZhengShunQian <zhengsq@xxxxxxxxxxxxxx> Base on nvmem framework, this series patches implement the eFuse driver of Rockchip SoC. The data from eFuse contains CPU leakage, chip code and version etc. The flow of reading data from eFuse is quite simple, configure the CTRL register, write data address to CTRL register, then data is available in DOUT register. The changes versus V0: 1. Enable/disable clock when required. 2. Split the drivers patch into three patches. 3. Update the docs of eFuse. ZhengShunQian (5): clk: rockchip: rk3288: Add the clock id of eFuse nvmem: fix the out-of-range leak in read/write() nvmem: rockchip-efuse: implement efuse driver Documentation: rockchip-efuse: describe the usage of eFuse ARM: dts: rockchip: add eFuse config of rk3288 SoC .../devicetree/bindings/nvmem/rockchip-efuse.txt | 38 ++++ arch/arm/boot/dts/rk3288.dtsi | 13 ++ drivers/clk/rockchip/clk-rk3288.c | 2 +- drivers/nvmem/Kconfig | 10 ++ drivers/nvmem/Makefile | 2 + drivers/nvmem/core.c | 4 +- drivers/nvmem/rockchip-efuse.c | 193 +++++++++++++++++++++ include/dt-bindings/clock/rk3288-cru.h | 1 + 8 files changed, 260 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/nvmem/rockchip-efuse.txt create mode 100644 drivers/nvmem/rockchip-efuse.c -- 1.9.1
