Thomas, On Mon, Sep 22, 2014 at 10:25 PM, Thomas Abraham <ta.omasab at gmail.com> wrote: > In the samsung cpuclk implementation, the ratio between PLL output and > armclk is always 1:1. So the divider that divides the PLL output to > get the armclk clock is always set to zero (div by 1). That divider > gets a non-zero value only when using an alternate parent clock source > during rate change operations. The dividers we're discussing here are extra dividers. In exynos speak this would be things like "CPUD", "ATB", "PCLK_DBG". -Doug
