On 09/23/2014 10:55 AM, jinkun.hong wrote:
> From: "jinkun.hong" <jinkun.hong at rock-chips.com>
Any summary for rk3288 power controller?
Maybe you can say something about how rk3288 TRM described this module.
> Signed-off-by: Jack Dai <jack.dai at rock-chips.com>
> Signed-off-by: Wang Caesar <caesar.wang at rock-chips.com>
> Signed-off-by: jinkun.hong <jinkun.hong at rock-chips.com>
>
> ---
>
> arch/arm/boot/dts/rk3288.dtsi | 45 +++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 45 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
> index 3bb5230..714b9d9 100644
> --- a/arch/arm/boot/dts/rk3288.dtsi
> +++ b/arch/arm/boot/dts/rk3288.dtsi
> @@ -15,6 +15,7 @@
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/pinctrl/rockchip.h>
> #include <dt-bindings/clock/rk3288-cru.h>
> +#include <dt-bindings/power-domain/rk3288.h>
> #include "skeleton.dtsi"
>
> / {
> @@ -467,6 +468,50 @@
> compatible = "rockchip,rk3288-pmu", "syscon";
> reg = <0xff730000 0x100>;
> };
> + power: power-controller {
> + compatible = "rockchip,rk3288-power-controller";
> + #power-domain-cells = <1>;
> + rockchip,pmu = <&pmu>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + pd_gpu {
> + reg = <RK3288_PD_GPU>;
> + clocks = <&cru ACLK_GPU>;
> + };
> +
> + pd_vio {
> + reg = <RK3288_PD_VIO>;
> + clocks = <&cru HCLK_RGA>, <&cru HCLK_VOP0>,
> + <&cru HCLK_VOP1>, <&cru HCLK_VIO_AHB_ARBI>,
> + <&cru HCLK_VIO_NIU>, <&cru HCLK_VIP>,
> + <&cru HCLK_IEP>, <&cru HCLK_ISP>,
> + <&cru HCLK_VIO2_H2P>, <&cru PCLK_MIPI_DSI0>,
> + <&cru PCLK_MIPI_DSI1>, <&cru PCLK_MIPI_CSI>,
> + <&cru PCLK_LVDS_PHY>, <&cru PCLK_EDP_CTRL>,
> + <&cru PCLK_HDMI_CTRL>, <&cru PCLK_VIO2_H2P>,
> + <&cru ACLK_VOP0>, <&cru ACLK_IEP>,
> + <&cru ACLK_VIO0_NIU>, <&cru ACLK_VIP>,
> + <&cru ACLK_VOP1>, <&cru ACLK_ISP>,
> + <&cru ACLK_VIO1_NIU>, <&cru ACLK_RGA>,
> + <&cru ACLK_RGA_NIU>,<&cru SCLK_RGA>,
> + <&cru DCLK_VOP0>, <&cru DCLK_VOP1>,
> + <&cru SCLK_EDP_24M>, <&cru SCLK_EDP>,
> + <&cru SCLK_ISP>, <&cru SCLK_ISP_JPE>,
> + <&cru SCLK_HDMI_HDCP>, <&cru SCLK_HDMI_CEC>;
> + };
Some of clock id here is not in upstream or list, I will send the patch
including all these clock IDs later, maybe you should mention it in your
commit message?
> +
> + pd_video {
> + reg = <RK3288_PD_VIDEO>;
> + /* FIXME: add clocks */
> + };
> +
> + pd_hevc {
> + reg = <RK3288_PD_HEVC>;
> + clocks = <&cru ACLK_HEVC>, <&cru HCLK_HEVC>,
> + <&cru SCLK_HEVC_CABAC>, <&cru SCLK_HEVC_CORE>;
> + };
> + };
>
> sgrf: syscon at ff740000 {
> compatible = "rockchip,rk3288-sgrf", "syscon";
