Heiko, On Wed, Sep 17, 2014 at 3:12 PM, Heiko Stuebner <heiko at sntech.de> wrote: > From: Doug Anderson <dianders at chromium.org> > > The Rockchip PLL code switches into slow mode (AKA bypass more AKA > 24MHz mode) before actually changing the PLL. This keeps anyone from > using the PLL while it's changing. However, in all known Rockchip > SoCs nobody should ever see the 24MHz when changing the PLL supplying > the armclk because we should reparent children to an alternate > (faster than 24MHz) PLL. > > One problem is that the code to switch to an alternate parent was > running in PRE_RATE_CHANGE. ...and the code to switch to slow mode > was _also_ running in PRE_RATE_CHANGE. That meant there was no real > guarantee that we would switch to an alternate parent before switching > to 24MHz mode. > > Let's move the switch to "slow mode" straight into > rockchip_rk3066_pll_set_rate(). That means we're guaranteed that the > 24MHz is really a last-resort. > > Note that without this change on real systems we were the code to > switch to an alternate parent at 24MHz. In some older versions of > that code we'd appy a (temporary) / 5 to the 24MHz causing us to run > at 4.8MHz. That wasn't enough to service USB interrupts in some cases > and could lead to a system hang. > > Signed-off-by: Doug Anderson <dianders at chromium.org> > Reviewed-by: Heiko Stuebner <heiko at sntech.de> > --- > drivers/clk/rockchip/clk-pll.c | 63 +++++++++--------------------------------- > 1 file changed, 13 insertions(+), 50 deletions(-) Thanks for adding my patch to your series (with the proper commit message)! I think you need your SoB on the patch too. Andrew Morton pointed to the docs in another patch I was involved in. Specifically, you were "on the patch delivery". See Documentation/SubmittingPatches section 12 (and 13). -Doug
