Heiko, On Fri, Sep 12, 2014 at 3:30 PM, Heiko Stuebner <heiko at sntech.de> wrote: > Rockchip SoCs contain clocks tightly bound to the armclk, where the best > rate / divider is supplied by the vendor after careful measuring. > Often this ideal rate may be greater than the current rate. > > Therefore prevent the ccf from trying to set these dividers itself by > setting them to read-only. > > In the case of the rk3066, this also includes the aclk_cpu, which makes it > necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...) > into individual definitions for rk3066 and rk3188. > > Signed-off-by: Heiko Stuebner <heiko at sntech.de> > --- > drivers/clk/rockchip/clk-rk3188.c | 26 ++++++++++++++++++-------- > drivers/clk/rockchip/clk-rk3288.c | 18 +++++++++--------- > 2 files changed, 27 insertions(+), 17 deletions(-) This seems pretty reasonable to me. I only glanced at rk3188 / rk3066 code quickly, but for rk3288 I can say: Reviewed-by: Doug Anderson <dianders at chromium.org> Tested-by: Doug Anderson <dianders at chromium.org>
