hi, On Wed, Dec 24, 2014 at 11:11 PM, Heiko St?bner <heiko at sntech.de> wrote: > The bit locations indicating the locking status of the plls on rk3066 are > shifted by one to the right when compared to the rk3188, bits [7:4] instead > of [8:5] on the rk3188, thus indicating the locking state of the wrong pll > or a completely different information in case of the gpll. > > The recently introduced pll init code exposed that problem on some rk3066 > boards when it tried to bring the boot-pll value in line with the value > from the rate table. > > Fix this by defining separate pll definitions for rk3066 with the correct > locking indices. > > Signed-off-by: Heiko Stuebner <heiko at sntech.de> > --- > drivers/clk/rockchip/clk-rk3188.c | 15 +++++++++++++-- > 1 file changed, 13 insertions(+), 2 deletions(-) it worked fine on ChipSPARK Rayeager PX2(=RK3066) board, thanks! Tested-by: FUKAUMI Naoki <naobsd at gmail.com>
