Hi Philipp:
On 2014?12?03? 21:09, Philipp Zabel wrote:
> Hi Andy,
>
> Am Mittwoch, den 03.12.2014, 20:32 +0800 schrieb Andy Yan:
>>> My question is not about the available gates at the SoC level, but about
>>> the actual clock inputs from point of view of the HDMI TX IP.
>>>
>>> It could be that the hdmi_ctrl_clk gates all inputs to the module and
>>> bus clocks together. If so, you could just reuse "isfr" and "iahb" and
>>> set it to the same clock. If not, we'd need to think of something else.
>>> Unfortunately I don't have any Synopsys documentation of the HDMI TX at
>>> that level.
>> After confirming with the IC designer, we finally make clear that
>> Rockchip RK3288 almost use the same clock design with imx:
>> clk-----iahbclk, used for hdmi module and bus
>> hdcp_clk-----isfrclk, used for hdcp and i2cm
>> cecclk -----cecclk, but this clk can be gated on rockchip, this is
>> different with imx,
>> but we don't handle the cec stuff now. So i will try to reuse the
>> imx clk binds. do you
>> think that is ok?
> Thank you for taking the time to verify this. So we should move the
> clock handling out of the soc specific parts into the common driver and
> reuse the existing clock bindings ("iahb", "isfr").
> I'd suggest to add the "cec" clock now to the binding document as an
> optional clock, then you can already specify it in the rockchip dtsi.
ok
>
> regards
> Philipp
>
>
>
