On Fri, 21 Feb 2025 16:55:15 +0100, Tommaso Merciai wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > The MIPI CSI-2 block on the Renesas RZ/V2H(P) SoC is similar to the one > found on the Renesas RZ/G2L SoC, with the following differences: > - A different D-PHY > - Additional registers for the MIPI CSI-2 link > - Only two clocks > > Add a new compatible string, `renesas,r9a09g057-csi2`, for the RZ/V2H(P) > SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx> > --- > Changes since v1: > - Dropped empty line as suggested by LPinchart > - Fixed minItems into else conditional block as suggested by RHerring > > .../bindings/media/renesas,rzg2l-csi2.yaml | 59 ++++++++++++++----- > 1 file changed, 44 insertions(+), 15 deletions(-) > Reviewed-by: Rob Herring (Arm) <robh@xxxxxxxxxx>
