[GIT PULL] clk: renesas: Updates for v6.15

[Geert Uytterhoeven <geert+renesas@xxxxxxxxx>]

	Hi Mike, Stephen,

The following changes since commit 2014c95afecee3e76ca4a56956a936e23283f05b:

  Linux 6.14-rc1 (2025-02-02 15:39:26 -0800)

are available in the Git repository at:

  git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.15-tag1

for you to fetch changes up to 9b12504e8c8c2f1f7e5f16afdd829603dd0c9508:

  clk: renesas: r9a09g047: Add CANFD clocks and resets (2025-02-20 17:42:03 +0100)

----------------------------------------------------------------
clk: renesas: Updates for v6.15

  - Add thermal (TSU) clock, reset, and power domain on RZ/G3S,
  - Add AI accelerator (DRP-AI) clocks and reset on RZ/V2L,
  - Add Image Signal Processor (ISP, FCPVX, VSPX) clocks on R-Car V3U,
    V4H, and V4M,
  - Add Watchdog (WDT), SDHI, Interrupt Controller (ICU), Camera (CRU0),
    and CAN-FD clocks and resets on RZ/G3E,
  - Miscellaneous fixes and improvements.

Thanks for pulling!

----------------------------------------------------------------
Biju Das (4):
      clk: renesas: r9a09g047: Add WDT clocks and resets
      clk: renesas: r9a09g047: Add SDHI clocks/resets
      clk: renesas: r9a09g047: Add ICU clock/reset
      clk: renesas: r9a09g047: Add CANFD clocks and resets

Claudiu Beznea (2):
      clk: renesas: r9a08g045: Add clocks, resets and power domain support for the TSU IP
      clk: renesas: r8a08g045: Check the source of the CPU PLL settings

Lad Prabhakar (5):
      clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validation
      clk: renesas: r9a07g044: Add clock and reset entry for DRP-AI
      clk: renesas: r9a07g043: Fix HP clock source for RZ/Five
      clk: renesas: rzg2l: Update error message
      clk: renesas: rzv2h: Update error message

Niklas Söderlund (6):
      clk: renesas: r8a779a0: Add FCPVX clocks
      clk: renesas: r8a779a0: Add ISP core clocks
      clk: renesas: r8a779g0: Add ISP core clocks
      clk: renesas: r8a779h0: Add ISP core clocks
      clk: renesas: r8a779h0: Add FCPVX clock
      clk: renesas: r8a779h0: Add VSPX clock

Tommaso Merciai (1):
      clk: renesas: r9a09g047: Add CRU0 clocks and resets

 drivers/clk/renesas/r8a779a0-cpg-mssr.c |   8 +++
 drivers/clk/renesas/r8a779g0-cpg-mssr.c |   2 +
 drivers/clk/renesas/r8a779h0-cpg-mssr.c |   3 +
 drivers/clk/renesas/r9a07g043-cpg.c     |   7 ++
 drivers/clk/renesas/r9a07g044-cpg.c     |  55 ++++++++++++++-
 drivers/clk/renesas/r9a08g045-cpg.c     |   9 ++-
 drivers/clk/renesas/r9a09g047-cpg.c     |  83 ++++++++++++++++++++++
 drivers/clk/renesas/rzg2l-cpg.c         | 119 ++++++++++++++++++--------------
 drivers/clk/renesas/rzg2l-cpg.h         |  12 +++-
 drivers/clk/renesas/rzv2h-cpg.c         |   4 +-
 10 files changed, 242 insertions(+), 60 deletions(-)

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds

Thanks for pulling!

Gr{oetje,eeting}s,

						Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
							    -- Linus Torvalds