Hi Thomas Gleixner, Geert, > -----Original Message----- > From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Sent: 12 February 2025 11:12 > Subject: [PATCH v5 10/12] irqchip/renesas-rzv2h: Drop TSSR_TIEN macro > > On RZ/G3E, TIEN bit position is at 15 compared to 7 on RZ/V2H. The macro > ICU_TSSR_TIEN(n) can be replaced with the inline logic BIT(field_width - 1) << (n * fieldwidth) for > supporting both SoCs. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > --- > v4->v5: > * Shortened tssr calculation in rzv2h_tint_irq_endisable(). > * Added tssr_shift_factor variable for optimizing the calculation > in rzv2h_tint_set_type() as the next patch uses the same factor. > v4: > * New patch > --- > drivers/irqchip/irq-renesas-rzv2h.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) > > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c > index 98a6a7cd3611..3635597ae4c1 100644 > --- a/drivers/irqchip/irq-renesas-rzv2h.c > +++ b/drivers/irqchip/irq-renesas-rzv2h.c > @@ -66,7 +66,6 @@ > > #define ICU_TSSR_TSSEL_PREP(tssel, n) ((tssel) << ((n) * 8)) > #define ICU_TSSR_TSSEL_MASK(n) ICU_TSSR_TSSEL_PREP(0x7F, n) > -#define ICU_TSSR_TIEN(n) (BIT(7) << ((n) * 8)) Please let me know, instead I should retain this macro with[1] and see changes below inlined?? #define ICU_TSSR_TIEN(mask, n, shift) ((mask) << ((n) * (shift))) > > #define ICU_TITSR_K(tint_nr) ((tint_nr) / 16) > #define ICU_TITSR_TITSEL_N(tint_nr) ((tint_nr) % 16) > @@ -153,9 +152,9 @@ static void rzv2h_tint_irq_endisable(struct irq_data *d, bool enable) > guard(raw_spinlock)(&priv->lock); > tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(k)); > if (enable) > - tssr |= ICU_TSSR_TIEN(tssel_n); > + tssr |= BIT((tssel_n + 1) * priv->info->field_width - 1); tssr |= ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width); > else > - tssr &= ~ICU_TSSR_TIEN(tssel_n); > + tssr &= ~(BIT((tssel_n + 1) * priv->info->field_width - 1)); tssr &= ~ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width); > writel_relaxed(tssr, priv->base + priv->info->t_offs + ICU_TSSR(k)); } > > @@ -277,6 +276,7 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > u32 titsr, titsr_k, titsel_n, tien; > struct rzv2h_icu_priv *priv; > u32 tssr, tssr_k, tssel_n; > + u32 tssr_shift_factor; > unsigned int hwirq; > u32 tint, sense; > int tint_nr; > @@ -314,7 +314,8 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > nr_tint = 32 / priv->info->field_width; > tssr_k = tint_nr / nr_tint; > tssel_n = tint_nr % nr_tint; > - tien = ICU_TSSR_TIEN(tssel_n); tien = ICU_TSSR_TIEN(priv->info->field_width - 1, tssel_n, priv->info->field_width); Cheers, Biju
