On 2/7/25 2:36 PM, Biju Das wrote: > On RZ/G3E, TSSEL register field is 8 bits wide compared to 7 on RZ/V2H. > Also bits 8..14 is reserved on RZ/G3E and any writes on these reserved > bits is ignored. Use the bitmask GENMASK(field_width - 2, 0) on both SoCs > for extracting TSSEL and we can drop the macros ICU_TSSR_TSSEL_PREP and > ICU_TSSR_TSSEL_MASK. > > Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> [...] > diff --git a/drivers/irqchip/irq-renesas-rzv2h.c b/drivers/irqchip/irq-renesas-rzv2h.c > index 6d1de9277c7d..71d06820e598 100644 > --- a/drivers/irqchip/irq-renesas-rzv2h.c > +++ b/drivers/irqchip/irq-renesas-rzv2h.c [...] > @@ -321,8 +318,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type) > guard(raw_spinlock)(&priv->lock); > > tssr = readl_relaxed(priv->base + priv->info->t_offs + ICU_TSSR(tssr_k)); > - tssr &= ~(ICU_TSSR_TSSEL_MASK(tssel_n) | tien); > - tssr |= ICU_TSSR_TSSEL_PREP(tint, tssel_n); > + tssr &= ~((GENMASK(priv->info->field_width - 2, 0) << > + (tssel_n * priv->info->field_width)) | tien); > + tssr |= (tint << (tssel_n * priv->info->field_width)); Don't need () around the |='s rvalue. [...] MBR, Sergey
