On Wed, Feb 5, 2025 at 10:10 AM Geert Uytterhoeven <geert+renesas@xxxxxxxxx> wrote: > > Disable support for ISA extensions that are not supported by RZ/Five: > - Svnapot extension support for supervisor mode NAPOT pages, > - Svpbmt extension support for supervisor mode page-based memory > types, > - VECTOR extension support, > - Zawrs extension support for more efficient busy waiting, > - Zba and Zbb extension support for bit manipulation instructions, > - Zbc extension support for carry-less multiplication > instructions, > - Zicboz extension support for faster zeroing of memory, > - T-Head vendor extension support. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- > Not intended for upstream merge. > To be applied to the topic/renesas-defconfig branch. > --- > arch/riscv/configs/rzfive_defconfig | 9 +++++++++ > 1 file changed, 9 insertions(+) > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Tested-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> Boot tested on v6.14-rc1 Cheers, Prabhakar > diff --git a/arch/riscv/configs/rzfive_defconfig b/arch/riscv/configs/rzfive_defconfig > index 14bb3fa1ed104d6e..b98acc93e3e37566 100644 > --- a/arch/riscv/configs/rzfive_defconfig > +++ b/arch/riscv/configs/rzfive_defconfig > @@ -31,7 +31,16 @@ CONFIG_ARCH_RENESAS=y > CONFIG_ERRATA_SIFIVE=y > CONFIG_NONPORTABLE=y > # CONFIG_RISCV_ISA_SUPM is not set > +# CONFIG_RISCV_ISA_SVNAPOT is not set > +# CONFIG_RISCV_ISA_SVPBMT is not set > +# CONFIG_RISCV_ISA_V is not set > +# CONFIG_RISCV_ISA_ZAWRS is not set > +# CONFIG_RISCV_ISA_ZBA is not set > +# CONFIG_RISCV_ISA_ZBB is not set > +# CONFIG_RISCV_ISA_ZBC is not set > # CONFIG_RISCV_ISA_ZICBOM is not set > +# CONFIG_RISCV_ISA_ZICBOZ is not set > +# CONFIG_RISCV_ISA_VENDOR_EXT_THEAD is not set > # CONFIG_EFI is not set > CONFIG_PM_AUTOSLEEP=y > CONFIG_CPU_IDLE=y > -- > 2.43.0 > >
