Hi Geert, Thanks for the feedback. > -----Original Message----- > From: Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> > Sent: 28 January 2025 15:17 > To: Biju Das <biju.das.jz@xxxxxxxxxxxxxx> > Subject: Re: [PATCH v3 01/13] dt-bindings: interrupt-controller: renesas,rzv2h-icu: Document RZ/G3E > SoC > > Hi Biju, > > Thanks for your patch! > > On Tue, 28 Jan 2025 at 11:47, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote: > > Document RZ/G3E (R9A09G047) ICU bindings. The ICU block on the RZ/G3E > > SoC is almost identical to the one found on the RZ/V2H SoC, with the > > following differences: > > - The TINT register offset is 0x830 compared to 0x30 on RZ/V2H. > > The first TINT register is at offset 0x820 vs. 0x20. > Perhaps: > > - The TINT register base offset is 0x800 instead of zero. OK, will fix this. > > > - The number of supported GPIO interrupts for TINT selection is 141 > > instead of 86. > > - The pin index and TINT selection index are not in the 1:1 map > > - The number of TSSR registers is 15 instead of 8 Will fix the typo 15->16 as you mentioned later. Cheers, Biju
