On 29/01/2025 17:37, Thierry Bultel wrote:
> Add the initial dtsi for the RZ/T2H Soc:
>
> - gic
> - armv8-timer
> - cpg clock
> - sci0 uart
>
> also add arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi, that keeps
> all 4 CPUs enabled, for consistency with later support of -m24
> and -m04 SoC revisions, that only have 2 and 1 Cortex-A55, respectively,
> and that will use /delete-node/ to disable the missing CPUs.
>
> Signed-off-by: Thierry Bultel <thierry.bultel.yh@xxxxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/renesas/r9a09g077.dtsi | 129 ++++++++++++++++++
> arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi | 8 ++
> 2 files changed, 137 insertions(+)
> create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> create mode 100644 arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
>
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> new file mode 100644
> index 000000000000..55a2b1bd8100
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077.dtsi
> @@ -0,0 +1,129 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#include <dt-bindings/clock/r9a09g077-cpg.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +
> +/ {
> + compatible = "renesas,r9a09g077";
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + extal: extal {
Use some generic clock names, prefixes or suffixes.
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + loco: loco {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + /* This value must be overridden by the board */
> + clock-frequency = <0>;
> + };
> +
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + L3_CA55: cache-controller-0 {
Labels are lowercase.
> + compatible = "cache";
> + cache-unified;
> + cache-size = <0x100000>;
> + cache-level = <3>;
> + };
...
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
> new file mode 100644
> index 000000000000..f54bb50829db
> --- /dev/null
> +++ b/arch/arm64/boot/dts/renesas/r9a09g077m44.dtsi
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +/*
> + * Device Tree Source for the RZ/T2H 4-core SoC
> + *
> + * Copyright (C) 2025 Renesas Electronics Corp.
> + */
> +
> +#include "r9a09g077.dtsi"
What is the point of this DTSI file? What is the point of your top-level
compatibles if you do not use them?
Best regards,
Krzysztof
