Hi Biju,
On Tue, 28 Jan 2025 at 11:48, Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> The ICU block on the RZ/G3E SoC is almost identical to the one found on
> the RZ/V2H SoC, with the following differences:
> - The TINT register offset starts at 0x830 instead of 0x30.
0x800
> - The number of GPIO interrupts for TINT selection is 141 instead of 86.
> - The pin index and TINT selection index are not in the 1:1 map
> - The number of TSSR registers is 15 instead of 8
16
> - Each TSSR register can program 2 TINTs instead of 4 TINTs
>
> Add support for the RZ/G3E driver by filling the rzv2h_hw_info table and
> adding LUT for mapping between pin index and TINT selection index.
>
> Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@xxxxxxxxxxxxxx>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Thanks for your patch!
> --- a/drivers/irqchip/irq-renesas-rzv2h.c
> +++ b/drivers/irqchip/irq-renesas-rzv2h.c
> @@ -84,6 +87,7 @@
> * @tssr_k: TSSR index k
> */
> struct rzv2h_hw_info {
> + const u8 *tssel_lut;
> u16 t_offs;
> u16 tien;
> u16 tssel_mask;
> @@ -307,6 +311,9 @@ static int rzv2h_tint_set_type(struct irq_data *d, unsigned int type)
> if (tint > priv->info->max_tssel)
> return -EINVAL;
>
> + if (priv->info->tssel_lut)
> + tint = priv->info->tssel_lut[tint & 0xff];
No need to mask with 0xff, because of the check above.
> +
> hwirq = irqd_to_hwirq(d);
> tint_nr = hwirq - ICU_TINT_START;
>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
