Hi Geert,
Thank you for the review.
On Thu, Jan 23, 2025 at 8:29 PM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> Thanks for your patch!
>
> On Wed, Jan 22, 2025 at 11:08 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > According to the Rev.1.20 hardware manual for the RZ/Five SoC, the clock
> > source for HP is derived from PLL6 divided by 2. This patch corrects the
> > implementation by configuring HP as a fixed clock source instead of a MUX.
> >
> > The `CPG_PL6_ETH_SSEL` register, which is available on the RZ/G2UL SoC, is
> > not present on the RZ/Five SoC, necessitating this change.
>
> While the register is not documented to exist, it reads back the same
> default value as on RZ/G2UL, selecting the right parent that does exist.
>
Yep.
> > Fixes: 95d48d270305ad2c ("clk: renesas: r9a07g043: Add support for RZ/Five SoC")
> > Cc: stable@xxxxxxxxxxxxxxx
> > Reported-by: Hien Huynh <hien.huynh.px@xxxxxxxxxxx>
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> > --- a/drivers/clk/renesas/r9a07g043-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> > @@ -138,7 +138,11 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
> > DEF_DIV("P2", R9A07G043_CLK_P2, CLK_PLL3_DIV2_4_2, DIVPL3A, dtable_1_32),
> > DEF_FIXED("M0", R9A07G043_CLK_M0, CLK_PLL3_DIV2_4, 1, 1),
> > DEF_FIXED("ZT", R9A07G043_CLK_ZT, CLK_PLL3_DIV2_4_2, 1, 1),
> > +#ifdef CONFIG_ARM64
> > DEF_MUX("HP", R9A07G043_CLK_HP, SEL_PLL6_2, sel_pll6_2),
>
> When building with W=1 on non-ARM64:
>
> error: ‘sel_pll6_2’ defined but not used
>
> so sel_pll6_2 [] needs to be protected by an #ifdef too (or __maybe_unused,
> but the rest of the file uses __ifdef).
>
Agreed, I'll use #ifdef for consistency.
> > +#else
>
> The rest of the file uses:
>
> #endif
> #ifdef CONFIG_RISCV
>
> instead of #else, so please use the same construct for consistency.
>
Sure, I'll update it as mentioned above.
Cheers,
Prabhakar
