RE: [PATCH 02/11] clk: renesas: r9a09g047: Add ICU clock/reset

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Hi Biju,

Thanks for your patch!

> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: 20 January 2025 09:47
> Subject: [PATCH 02/11] clk: renesas: r9a09g047: Add ICU clock/reset
> 
> Add ICU clock and reset entries.
> 
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>

Reviewed-by: Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>

Cheers,
Fab

> ---
>  drivers/clk/renesas/r9a09g047-cpg.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
> index 1886eab9ef9e..1181e7b605e8 100644
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -90,6 +90,8 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = {
>  };
> 
>  static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> +	DEF_MOD_CRITICAL("icu_0_pclk_i",	CLK_PLLCM33_DIV16, 0, 5, 0, 5,
> +						BUS_MSTOP_NONE),
>  	DEF_MOD_CRITICAL("gic_0_gicclk",	CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19,
>  						BUS_MSTOP(3, BIT(5))),
>  	DEF_MOD("wdt_1_clkp",			CLK_PLLCLN_DIV16, 4, 13, 2, 13,
> @@ -128,6 +130,7 @@ static const struct rzv2h_mod_clk r9a09g047_mod_clks[] __initconst = {
> 
>  static const struct rzv2h_reset r9a09g047_resets[] __initconst = {
>  	DEF_RST(3, 0, 1, 1),		/* SYS_0_PRESETN */
> +	DEF_RST(3, 6, 1, 7),		/* ICU_0_PRESETN_I */
>  	DEF_RST(3, 8, 1, 9),		/* GIC_0_GICRESET_N */
>  	DEF_RST(3, 9, 1, 10),		/* GIC_0_DBG_GICRESET_N */
>  	DEF_RST(7, 6, 3, 7),		/* WDT_1_RESET */
> --
> 2.43.0
> 






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