On Wed, Jan 15, 2025 at 3:21 PM Claudiu <claudiu.beznea@xxxxxxxxx> wrote:
> From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
>
> On the RZ/G3S SoC, the CPU PLL settings can be set and retrieved through
> the CPG_PLL1_CLK1 and CPG_PLL1_CLK2 registers. However, these settings are
> applied only when CPG_PLL1_SETTING.SEL_PLL1 is set to 0. Otherwise, the
> CPU PLL operates at the default frequency of 1.1 GHz. This patch adds
> support to the PLL driver to return the 1.1 GHz frequency when the CPU PLL
> is configured with the default frequency.
>
> Fixes: 01eabef547e6 ("clk: renesas: rzg2l: Add support for RZ/G3S PLL")
> Fixes: de60a3ebe410 ("clk: renesas: Add minimal boot support for RZ/G3S SoC")
> Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
i.e. will queue in renesas-clk for v6.15.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
