Re: [PATCH] ARM: cacheinfo fix format field mask

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

Hi Dmitry,

Thanks for your patch!

On Wed, Jan 15, 2025 at 12:11 PM Dmitry Baryshkov
<dmitry.baryshkov@xxxxxxxxxx> wrote:
> Fix C&P error left unnoticed during the reviews. The FORMAT field spans
> over bits 29-31, not 24-27 of the CTR register.

Please add

    This causes a warning on e.g. Cortex-A8 and Cortex-A9:

        WARNING: CPU: 0 PID: 0 at arch/arm/kernel/cacheinfo.c:43
cache_line_size+0x84/0x94

so people find this patch when looking up the warning.

> Fixes: a9ff94477836 ("ARM: 9433/2: implement cacheinfo support")
> Reported-by: Marek Szyprowski <m.szyprowski@xxxxxxxxxxx>
> Closes: https://lore.kernel.org/linux-arm-msm/01515ea0-c6f0-479f-9da5-764d9ee79ed6@xxxxxxxxxxx/
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>

This fixes the warning on Cortex-A8/A9, so
Tested-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>

Note that this changes HWalign on Cortex-A9 (various Renesas SoCs,
with 1, 2, or 4 CPU cores):

    -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1
    +SLUB: HWalign=32, Order=0-3, MinObjects=0, CPUs=<N>, Nodes=1

On Cortex-A8 (BeagleBone Black, i.e. AM335x), it changes HWalign,
and causes a warning message:

    -SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
    +SLUB: HWalign=16, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
     ...
    +cacheinfo: Unable to detect cache hierarchy for CPU 0

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds