Hi Prabhakar,
On Fri, Jan 10, 2025 at 12:52 PM Lad, Prabhakar
<prabhakar.csengg@xxxxxxxxx> wrote:
> On Fri, Jan 10, 2025 at 11:30 AM Geert Uytterhoeven
> <geert@xxxxxxxxxxxxxx> wrote:
> > On Tue, Jan 7, 2025 at 11:59 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> > >
> > > Make the PFC mask for the PFC_mx register configurable to address
> > > differences between SoCs in the RZ/G2L family and RZ/V2H.
> >
> > "and the RZ/V2h family", as RZ/G3E is also affected.
> >
> > > On RZ/G2L family SoCs, the PFC_mx mask is `0x7` (3 bits), while on RZ/V2H
> > > it is `0xf` (4 bits). The previous implementation hardcoded the PFC mask
> > > as `0x7`, which caused incorrect behavior when configuring PFC registers
> > > on RZ/V2H.
> > >
> > > To resolve this, introduce a `pfcmask` field in the `rzg2l_hwcfg` structure
> > > to make the mask value configurable based on the SoC. Update PFC-related
> > > logic to use `hwcfg->pfcmask` instead of a hardcoded value. Additionally,
> > > update hardware configuration definitions to include the appropriate mask
> > > values (`0x7` for RZ/G2L family and `0xf` for RZ/V2H).
> >
> > i understand this means that SD1_CD has always been broken:
> >
> Yea, but since the TF-A configured it we didnt see an issue.
>
> > arch/arm64/boot/dts/renesas/r9a09g057h44-rzv2h-evk.dts:
> > pinmux = <RZV2H_PORT_PINMUX(9, 4, 14)>; /* SD1_CD */
> >
> > and this should be queued as a fix, and backported to v6.12?
> >
> Agreed.
If there is currently no issue, there is no reason to hurry, and
queuing for v6.14 (+ backporting) should be fine.
Postponing to v6.15 might cause issues if a new user of functions 8-15
is added to DTS in the next cycle.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
