[PATCH v3 0/6] Fix MSTOP handling and add SYS/GIC clock entries for RZ/V2H(P) SoC

[Prabhakar <prabhakar.csengg@xxxxxxxxx>]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>

Hi All,

This patch series fixes MSTOP handling in the RZ/V2H CPG family driver
and add support for clock and reset entries for GIC and SYS, along with
some cleanup.

v2->v3
- Included RB tag from Geert
- Dropped unnecessary parentheses
- Fixed review comments from Geert for patch 4/6

v1->v2
- Updated commit description in patch 1/6
- Updated fixes tag commit header in patch 1/6
- Introduced new patch to support mstop configuration per-bit
  instead of group based

Cheers,
Prabhakar

Lad Prabhakar (6):
  clk: renesas: rzv2h: Fix use-after-free in MSTOP refcount handling
  clk: renesas: rzv2h: Relocate MSTOP-related macros to the family
    driver
  clk: renesas: rzv2h: Simplify BUS_MSTOP macros and field extraction
  clk: renesas: rzv2h: Switch MSTOP configuration to per-bit basis
  clk: renesas: r9a09g057: Add reset entry for SYS
  clk: renesas: r9a09g057: Add clock and reset entries for GIC

 drivers/clk/renesas/r9a09g047-cpg.c |   2 +
 drivers/clk/renesas/r9a09g057-cpg.c |   7 ++
 drivers/clk/renesas/rzv2h-cpg.c     | 185 +++++++++++++++-------------
 drivers/clk/renesas/rzv2h-cpg.h     |  13 +-
 4 files changed, 116 insertions(+), 91 deletions(-)

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2.43.0