On Tue, Dec 3, 2024 at 11:50 AM Biju Das <biju.das.jz@xxxxxxxxxxxxxx> wrote:
> The clock structure for RZ/G3E is almost identical to RZ/V2H SoC with
> more IP blocks compared to RZ/V2H. For eg: VSPI, LVDS, DPI and LCDC1
> are present only on the RZ/G3E SoC.
>
> Add minimal clock and reset entries required to boot the Renesas RZ/G3E
> SMARC EVK and binds it with the RZ/V2H CPG core driver.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
