Hi John,
Thanks for the patch.
> -----Original Message-----
> From: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> Sent: 06 December 2024 21:26
> Subject: [PATCH 3/5] soc: renesas: rz-sysc: Add support for RZ/G3E family
>
> Add SoC detection support for RZ/G3E SoC. Also add support for detecting the number of cores and
> ETHOS-U55 NPU and also detect PLL mismatch for SW settings other than 1.7GHz.
>
> Signed-off-by: John Madieu <john.madieu.xa@xxxxxxxxxxxxxx>
> ---
>
> data = match->data;
> - if (!data->max_register_offset)
> - return -EINVAL;
> + if (data->signals_init_data) {
> + if (!data->max_register_offset)
> + return -EINVAL;
>
> - ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals);
> - if (ret)
> - return ret;
> + ret = rz_sysc_signals_init(sysc, data->signals_init_data, data->num_signals);
> + if (ret)
> + return ret;
> +
> + rz_sysc_regmap.max_register = data->max_register_offset;
> + dev_set_drvdata(dev, sysc);
>
> - dev_set_drvdata(dev, sysc);
> - rz_sysc_regmap.max_register = data->max_register_offset;
> - regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap);
> - if (IS_ERR(regmap))
> - return PTR_ERR(regmap);
> + regmap = devm_regmap_init(dev, NULL, sysc, &rz_sysc_regmap);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
>
> - return of_syscon_register_regmap(dev->of_node, regmap);
> + return of_syscon_register_regmap(dev->of_node, regmap);
Basically if I understand correctly, you are going to use normal
Syscon call for register access in PCIe and TSU drivers. Is it correct?
For example,
priv->syscon = syscon_regmap_lookup_by_phandle(np, "syscon");
regmap_read(priv->syscon,xxx)
Cheers,
Biju
> + }
> +
> + return 0;
> }
>
> static struct platform_driver rz_sysc_driver = { diff --git a/drivers/soc/renesas/rz-sysc.h
> b/drivers/soc/renesas/rz-sysc.h index babca9c743c7..2b5ad41cef9e 100644
> --- a/drivers/soc/renesas/rz-sysc.h
> +++ b/drivers/soc/renesas/rz-sysc.h
> @@ -8,7 +8,9 @@
> #ifndef __SOC_RENESAS_RZ_SYSC_H__
> #define __SOC_RENESAS_RZ_SYSC_H__
>
> +#include <linux/device.h>
> #include <linux/refcount.h>
> +#include <linux/sys_soc.h>
> #include <linux/types.h>
>
> /**
> @@ -42,6 +44,7 @@ struct rz_sysc_signal {
> * @offset: SYSC SoC ID register offset
> * @revision_mask: SYSC SoC ID revision mask
> * @specific_id_mask: SYSC SoC ID specific ID mask
> + * @extended_device_identification: SoC-specific extended device
> + identification
> */
> struct rz_sysc_soc_id_init_data {
> const char * const family;
> @@ -49,6 +52,9 @@ struct rz_sysc_soc_id_init_data {
> u32 offset;
> u32 revision_mask;
> u32 specific_id_mask;
> + void (*extended_device_identification)(struct device *dev,
> + void __iomem *sysc_base,
> + struct soc_device_attribute *soc_dev_attr);
> };
>
> /**
> @@ -65,6 +71,7 @@ struct rz_sysc_init_data {
> u32 max_register_offset;
> };
>
> +extern const struct rz_sysc_init_data rzg3e_sysc_init_data;
> extern const struct rz_sysc_init_data rzg3s_sysc_init_data;
>
> #endif /* __SOC_RENESAS_RZ_SYSC_H__ */
> --
> 2.25.1
