On Tue, Dec 03, 2024 at 01:13:11PM +0200, Claudiu wrote: > From: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> > > Document the ADC IP available on the RZ/G3S SoC. The ADC IP on the RZ/G3S > differs slightly from the one found on the RZ/G2L. The identified > differences are as follows: > - different number of channels (one being used for temperature conversion); > consequently, various registers differ; the temperature channel > support was not available for the RZ/G2L variant; the #io-channel-cells > property was added to be able to request the temperature channel from > the thermal driver > - different default sampling periods > - the RZ/G3S variant lacks the ADVIC register. > > Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Attachment:
signature.asc
Description: PGP signature
