Hi All,
> -----Original Message-----
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: 22 November 2024 12:46
> Subject: [PATCH 07/12] clk: renesas: rzv2h-cpg: Add MSTOP support
>
> Add bus MSTOP support for RZ/{V2H, G3E}. For some module clocks, there are no MSTOP bits and the
> sequence ordering for mstop and clock on is different compared to the RZ/G2L family.
>
> Signed-off-by: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> ---
> drivers/clk/renesas/r9a09g047-cpg.c | 6 +-
> drivers/clk/renesas/r9a09g057-cpg.c | 117 ++++++++++++++++++----------
> drivers/clk/renesas/rzv2h-cpg.c | 92 +++++++++++++++++++++-
> drivers/clk/renesas/rzv2h-cpg.h | 22 ++++--
> 4 files changed, 188 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/clk/renesas/r9a09g047-cpg.c b/drivers/clk/renesas/r9a09g047-cpg.c
> index 5d7611cee9bc..ab63a7e7e480 100644
> --- a/drivers/clk/renesas/r9a09g047-cpg.c
> +++ b/drivers/clk/renesas/r9a09g047-cpg.c
> @@ -69,8 +69,10 @@ static const struct cpg_core_clk r9a09g047_core_clks[] __initconst = { };
>
> static void __init
> rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
> struct rzv2h_cpg_priv *priv)
> @@ -552,6 +630,14 @@ rzv2h_cpg_register_mod_clk(const struct rzv2h_mod_clk *mod,
>
> priv->clks[id] = clock->hw.clk;
>
> + if (mod->mstop_data != BUS_MSTOP_NO_DATA) {
> + clock->mstop = rzv2h_cpg_get_mstop(priv, mod->mstop_data);
> + if (!clock->mstop) {
> + clock = ERR_PTR(-ENOMEM);
Typo this has to be clk = ERR_PTR(-ENOMEM);
Will fix this in next version
Cheers,
Biju
