Hi Geert > Early revisions of the R-Car V4M Series Hardware Userʼs Manual > contained an incorrect formula for the CPU core clocks: > > ZCnφ = (PLL2VCO x 1/2) x mult/32 > > Dang-san fixed this by using CLK_PLL2_DIV2 instead of CLK_PLL2 as the > parent clock. > > In Rev.0.70 of the documentation, the formula was corrected to: > > ZCnφ = (PLL2VCO x 1/4) x mult/32 > > As the CPG Block Diagram now shows a separate 1/4 post-divider for PLL2, > the use of CLK_PLL2_DIV2 is a recurring source of confusion. Hence get > rid of CLK_PLL2_DIV2, and include the proper 1/4 post-divider in the > invocation of the DEF_GEN4_Z() macro, like is done on other R-Car Gen4 > (and Gen3) SoCs. > > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> > --- Please add Reported-by: Vinh Nguyen <vinh.nguyen.xz@xxxxxxxxxxx> Thank you for your help !! Best regards --- Kuninori Morimoto
