Hi Prabhakar, > -----Original Message----- > From: Prabhakar <prabhakar.csengg@xxxxxxxxx> > Sent: Tuesday, October 8, 2024 5:50 PM > Subject: [PATCH v2] arm64: dts: renesas: r9a09g057: Add OPP table > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Add OPP table for RZ/V2H(P) SoC. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > --- > v1->v2 > - Set opp-microvolt to 800000 for frequencies below 1.1GHz > --- > arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 41 ++++++++++++++++++++++ > 1 file changed, 41 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > index 1ad5a1b6917f..4bbe75b81f54 100644 > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi > @@ -20,6 +20,39 @@ audio_extal_clk: audio-clk { > clock-frequency = <0>; > }; > > + /* > + * The default cluster table is based on the assumption that the PLLCA55 clock > + * frequency is set to 1.7GHz. The PLLCA55 clock frequency can be set to > + * 1.7/1.6/1.5/1.1 GHz based on the BOOTPLLCA_0/1 pins (and additionally can be > + * clocked to 1.8GHz as well). The table below should be overridden in the board > + * DTS based on the PLLCA55 clock frequency. > + */ > + cluster0_opp: opp-table-0 { > + compatible = "operating-points-v2"; > + > + opp-1700000000 { > + opp-hz = /bits/ 64 <1700000000>; > + opp-microvolt = <900000>; Not sure CA-55 can change voltage from 800mV to 900mV?? Based on Power Domain Control, it needs to be in AWO mode for changing the PD_CA55 voltage. The manual says OD voltage is 0.9V and ND voltage is 0.8V. Is 1.7GHZ is ND or OD? Cheers, Biju > + clock-latency-ns = <300000>; > + }; > + opp-850000000 { > + opp-hz = /bits/ 64 <850000000>; > + opp-microvolt = <800000>; > + clock-latency-ns = <300000>; > + }; > + opp-425000000 { > + opp-hz = /bits/ 64 <425000000>; > + opp-microvolt = <800000>; > + clock-latency-ns = <300000>; > + }; > + opp-212500000 { > + opp-hz = /bits/ 64 <212500000>; > + opp-microvolt = <800000>; > + clock-latency-ns = <300000>; > + opp-suspend; > + }; > + }; > + > cpus { > #address-cells = <1>; > #size-cells = <0>; > @@ -30,6 +63,8 @@ cpu0: cpu@0 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK0>; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu1: cpu@100 { > @@ -38,6 +73,8 @@ cpu1: cpu@100 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK1>; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu2: cpu@200 { > @@ -46,6 +83,8 @@ cpu2: cpu@200 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK2>; > + operating-points-v2 = <&cluster0_opp>; > }; > > cpu3: cpu@300 { > @@ -54,6 +93,8 @@ cpu3: cpu@300 { > device_type = "cpu"; > next-level-cache = <&L3_CA55>; > enable-method = "psci"; > + clocks = <&cpg CPG_CORE R9A09G057_CA55_0_CORE_CLK3>; > + operating-points-v2 = <&cluster0_opp>; > }; > > L3_CA55: cache-controller-0 { > -- > 2.43.0