Re: [PATCH v2 1/2] clk: renesas: rzv2h-cpg: Add support for dynamic switching divider clocks

[Geert Uytterhoeven <geert@xxxxxxxxxxxxxx>]

Hi Prabhakar,

On Thu, Aug 22, 2024 at 1:16 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add support for dynamic switching divider clocks.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> v1->v2
> - Dropped DDIV_DIVCTL_WIDTH
> - width is now extracted from conf
> - Updated DDIV_GET_* macros
> - Now doing rmw as some of the DIVCTLx require it

Thanks for the update!

> --- a/drivers/clk/renesas/rzv2h-cpg.c
> +++ b/drivers/clk/renesas/rzv2h-cpg.c
> @@ -45,14 +45,23 @@
>  #define PDIV(val)              FIELD_GET(GENMASK(5, 0), (val))
>  #define SDIV(val)              FIELD_GET(GENMASK(2, 0), (val))
>
> +#define DDIV_DIVCTL_WEN(shift)         (1 << ((shift) + 16))

BIT((shift) + 16)

> +#define DDIV_GET_WIDTH(val)            FIELD_GET(GENMASK(3, 0), (val))
> +#define DDIV_GET_SHIFT(val)            FIELD_GET(GENMASK(7, 4), (val))
> +#define DDIV_GET_REG_OFFSET(val)       FIELD_GET(GENMASK(18, 8), (val))
> +#define DDIV_GET_MON(val)              FIELD_GET(GENMASK(23, 19), (val))

These are not register fields, so you might as well just use C bitfields
accesses instead:

    struct ddiv {
            unsigned int width:4;
            unsigned int shift:4;
            unsigned int offset:11;
            unsigned int monbit:5;
    };

    if ((shift + core->ddiv.width > 16)
            return ERR_PTR(-EINVAL);

(you can put cpg_core_clk.conf and cpg_core_clk.ddiv in a union to save space)

The rest LGTM.

Gr{oetje,eeting}s,

                        Geert

-- 
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds