On Mon, Jul 15, 2024 at 2:56 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > Document the device tree bindings for the Renesas RZ/V2H(P) SoC > Clock Pulse Generator (CPG). > > CPG block handles the below operations: > - Generation and control of clock signals for the IP modules > - Generation and control of resets > - Control over booting > - Low power consumption and power supply domains > > Also define constants for the core clocks of the RZ/V2H(P) SoC. Note the > core clocks are a subset of the ones which are listed as part of section > 4.4.2 of HW manual Rev.1.01 which cannot be controlled by CLKON register. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx> > --- > v3->v4 > - Included RB tag form Krzysztof > - Changed reset and clock values to hex > - Renamed __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__ to > __DT_BINDINGS_CLOCK_RENESAS_R9A09G057_CPG_H__ Reviewed-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds