This patch enables PWM channels 1+2 on the GrayHawk board. Only for testing, not for upstream. Signed-off-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx> --- .../dts/renesas/r8a779h0-gray-hawk-single.dts | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts index 2b9a19bb1c5d..62878120673d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts +++ b/arch/arm64/boot/dts/renesas/r8a779h0-gray-hawk-single.dts @@ -199,6 +199,16 @@ mmc_pins: mmc { power-source = <1800>; }; + pwm1_pins: pwm1 { + groups = "pwm1_a"; + function = "pwm1"; + }; + + pwm2_pins: pwm2 { + groups = "pwm2_a"; + function = "pwm2"; + }; + qspi0_pins: qspi0 { groups = "qspi0_ctrl", "qspi0_data4"; function = "qspi0"; @@ -215,6 +225,20 @@ scif_clk2_pins: scif-clk2 { }; }; +&pwm1 { + pinctrl-0 = <&pwm1_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + +&pwm2 { + pinctrl-0 = <&pwm2_pins>; + pinctrl-names = "default"; + + status = "okay"; +}; + &rpc { pinctrl-0 = <&qspi0_pins>; pinctrl-names = "default"; -- 2.43.0