Hi Geert-san,
> From: Geert Uytterhoeven, Sent: Wednesday, June 12, 2024 4:25 PM
>
> The multipliers for PLL2 and PLL4 as listed in the comments for
> the cpg_pll_configs[] array are incorrect. Fix them.
>
> Note that the actual values in the tables were correct.
>
> Reported-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
> Fixes: f077cab34df3010d ("clk: renesas: cpg-mssr: Add support for R-Car V4M")
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Thank you for the patch!
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Best regards,
Yoshihiro Shimoda
> ---
> To be queued in renesas-clk for v6.11.
> ---
> drivers/clk/renesas/r8a779h0-cpg-mssr.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> index 0a553d5170d5fdde..1057a2b6a72769dd 100644
> --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> @@ -243,10 +243,10 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
> * MD EXTAL PLL1 PLL2 PLL3 PLL4 PLL5 PLL6 OSC
> * 14 13 (MHz)
> * ------------------------------------------------------------------------
> - * 0 0 16.66 / 1 x192 x204 x192 x144 x192 x168 /16
> - * 0 1 20 / 1 x160 x170 x160 x120 x160 x140 /19
> + * 0 0 16.66 / 1 x192 x240 x192 x240 x192 x168 /16
> + * 0 1 20 / 1 x160 x200 x160 x200 x160 x140 /19
> * 1 0 Prohibited setting
> - * 1 1 33.33 / 2 x192 x204 x192 x144 x192 x168 /32
> + * 1 1 33.33 / 2 x192 x240 x192 x240 x192 x168 /32
> */
> #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 13) | \
> (((md) & BIT(13)) >> 13))
> --
> 2.34.1
