On 30.05.2024 20:38, Prabhakar wrote:
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Fix the typo B0WI -> BOWI to match with the RZ/G2L HW manual.
>
> Reported-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Tested-by: Claudiu Beznea <claudiu.beznea.uj@xxxxxxxxxxxxxx> # on RZ/G3S
> ---
> v2->v3
> - New patch
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 18 +++++++++---------
> 1 file changed, 9 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index f784169abf11..169986022a73 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -131,7 +131,7 @@
> #define PVDD_1800 1 /* I/O domain voltage <= 1.8V */
> #define PVDD_3300 0 /* I/O domain voltage >= 3.3V */
>
> -#define PWPR_B0WI BIT(7) /* Bit Write Disable */
> +#define PWPR_BOWI BIT(7) /* Bit Write Disable */
> #define PWPR_PFCWE BIT(6) /* PFC Register Write Enable */
>
> #define PM_MASK 0x03
> @@ -478,8 +478,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> writeb(reg & ~BIT(pin), pctrl->base + PMC(off));
>
> /* Set the PWPR register to allow PFC register to write */
> - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> - writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
> + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */
> + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=1 */
>
> /* Select Pin function mode with PFC register */
> reg = readl(pctrl->base + PFC(off));
> @@ -487,8 +487,8 @@ static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl,
> writel(reg | (func << (pin * 4)), pctrl->base + PFC(off));
>
> /* Set the PWPR register to be write-protected */
> - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> - writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
> + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */
> + writel(PWPR_BOWI, pctrl->base + regs->pwpr); /* BOWI=1, PFCWE=0 */
>
> /* Switch to Peripheral pin function with PMC register */
> reg = readb(pctrl->base + PMC(off));
> @@ -2520,8 +2520,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
> const struct rzg2l_register_offsets *regs = &hwcfg->regs;
>
> /* Set the PWPR register to allow PFC register to write. */
> - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> - writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=1 */
> + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */
> + writel(PWPR_PFCWE, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=1 */
>
> /* Restore port registers. */
> for (u32 port = 0; port < nports; port++) {
> @@ -2565,8 +2565,8 @@ static void rzg2l_pinctrl_pm_setup_pfc(struct rzg2l_pinctrl *pctrl)
> }
>
> /* Set the PWPR register to be write-protected. */
> - writel(0x0, pctrl->base + regs->pwpr); /* B0WI=0, PFCWE=0 */
> - writel(PWPR_B0WI, pctrl->base + regs->pwpr); /* B0WI=1, PFCWE=0 */
> + writel(0x0, pctrl->base + regs->pwpr); /* BOWI=0, PFCWE=0 */
> + writel(PWPR_BOWI, pctrl->base + regs->pwpr); /* BOWI=1, PFCWE=0 */
> }
>
> static int rzg2l_pinctrl_suspend_noirq(struct device *dev)
