Hi Geert,
Thank you for the review.
On Mon, May 27, 2024 at 10:18 AM Geert Uytterhoeven
<geert@xxxxxxxxxxxxxx> wrote:
>
> Hi Prabhakar,
>
> On Fri, May 24, 2024 at 10:29 AM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote:
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> >
> > Define RZ/V2H(P) (R9A09G057) Clock Pulse Generator module clock outputs
> > (CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
> > in Section 4.4.2 and 4.4.3 ("List of Clock/Reset Signals") of the RZ/V2H(P)
> > Hardware User's Manual (Rev.1.01, Feb. 2024).
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Thanks for your patch!
>
> > --- /dev/null
> > +++ b/include/dt-bindings/clock/r9a09g057-cpg.h
> > @@ -0,0 +1,644 @@
> > +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > + *
> > + * Copyright (C) 2024 Renesas Electronics Corp.
> > + */
> > +#ifndef __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > +#define __DT_BINDINGS_CLOCK_R9A09G057_CPG_H__
> > +
> > +#include <dt-bindings/clock/renesas-cpg-mssr.h>
> > +
> > +/* Clock list */
>
> No distinction between Core and Module clocks?
>
I was in two minds here. Would you prefer clocks with no CGC support
to be listed as core clocks?
> > +#define R9A09G057_SYS_0_PCLK 0
> > +#define R9A09G057_DMAC_0_ACLK 1
> > +#define R9A09G057_DMAC_1_ACLK 2
> > +#define R9A09G057_DMAC_2_ACLK 3
>
> [...]
>
> > +/* Resets list */
>
> [...]
>
> No power domain specifiers, as mentioned in PATCH 1/4?
>
OK, I'll add the power domains in this patch.
Cheers,
Prabhakar
