Re: [PATCH 1/3] clk: renesas: r8a779h0: Add VIN clocks

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Hi Geert,

Thanks for your review.

On 2024-05-29 17:01:20 +0200, Geert Uytterhoeven wrote:
> Hi Niklas,
> 
> On Mon, May 27, 2024 at 3:16 PM Niklas Söderlund
> <niklas.soderlund+renesas@xxxxxxxxxxxx> wrote:
> > Add the VIN module clocks, which are used by the VIN modules on the
> > Renesas R-Car V4M (R8A779H0) SoC.
> >
> > Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> 
> Thanks for your patch!
> 
> > --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> > +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> > @@ -188,6 +188,22 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
> >         DEF_MOD("sdhi0",        706,    R8A779H0_CLK_SD0),
> >         DEF_MOD("sydm1",        709,    R8A779H0_CLK_S0D6_PER),
> >         DEF_MOD("sydm2",        710,    R8A779H0_CLK_S0D6_PER),
> > +       DEF_MOD("vin0",         730,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin1",         731,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin2",         800,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin3",         801,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin4",         802,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin5",         803,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin6",         804,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin7",         805,    R8A779H0_CLK_S0D1_VIO),
> 
> According to the documentation for the Module Stop Control Registers
> 7 and 8, these are called "vin0[1-7]" instead of "vin[1-7]".

Will fix.

> 
> > +       DEF_MOD("vin10",        806,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin11",        807,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin12",        808,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin13",        809,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin14",        810,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin15",        811,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin16",        812,    R8A779H0_CLK_S0D1_VIO),
> > +       DEF_MOD("vin17",        813,    R8A779H0_CLK_S0D1_VIO),
> 
> According to Table 8.1.4a ("Lists of CPG clocks generated from PLL1")
> the parent clock is S0D4_VIO.

Will fix.

> 
> >         DEF_MOD("wdt1:wdt0",    907,    R8A779H0_CLK_R),
> >         DEF_MOD("pfc0",         915,    R8A779H0_CLK_CP),
> >         DEF_MOD("pfc1",         916,    R8A779H0_CLK_CP),
> 
> Gr{oetje,eeting}s,
> 
>                         Geert
> 
> -- 
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
> 
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds

-- 
Kind Regards,
Niklas Söderlund




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