Add the device node for the Interrupt Controller for External Devices
(INTC-EX) on the Renesas R-Car V4M (R8A779H0) SoC, which serves external
IRQ pins IRQ[0-5].
Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
---
IRQ2 was tested on the Gray Hawk Single development board using
gpio-keys. With the default hardware setup, this causes an interrupt
storm, as expected (pin is shared with MD0).
To be queued in renesas-devel for v6.10.
---
arch/arm64/boot/dts/renesas/r8a779h0.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
index 530219f21295f76f..bd3955316a88c8f2 100644
--- a/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779h0.dtsi
@@ -404,6 +404,22 @@ tsc: thermal@e6198000 {
#thermal-sensor-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a779h0", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 611>;
+ power-domains = <&sysc R8A779H0_PD_ALWAYS_ON>;
+ resets = <&cpg 611>;
+ };
+
tmu0: timer@e61e0000 {
compatible = "renesas,tmu-r8a779h0", "renesas,tmu";
reg = <0 0xe61e0000 0 0x30>;
--
2.34.1
