From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
This patch introduces function pointers, read_oen() and write_oen(), in the
struct rzg2l_pinctrl_data to facilitate reading and writing to the PFC_OEN
register. On the RZ/V2H SoC, unlocking the PWPR.REGWE_B bit before writing
to the PFC_OEN register is necessary, and the PFC_OEN register has more
bits compared to the RZ/G2L family. To handle these differences between
RZ/G2L and RZ/V2H and to reuse the existing code for RZ/V2H, these function
pointers are introduced.
Additionally, this patch populates these function pointers with appropriate
data for existing SoCs.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
---
drivers/pinctrl/renesas/pinctrl-rzg2l.c | 12 ++++++++++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
index 3de97d5e198a..9bc110b00cbb 100644
--- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
+++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
@@ -261,6 +261,8 @@ struct rzg2l_pinctrl_data {
void (*set_pfc_mode)(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func);
void (*pm_set_pfc)(struct rzg2l_pinctrl *pctrl);
void (*pmc_writeb)(struct rzg2l_pinctrl *pctrl, u8 val, void __iomem *addr);
+ u32 (*read_oen)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin);
+ int (*write_oen)(struct rzg2l_pinctrl *pctrl, u32 caps, u32 offset, u8 pin, u8 oen);
};
/**
@@ -1120,7 +1122,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev,
break;
case PIN_CONFIG_OUTPUT_ENABLE:
- arg = rzg2l_read_oen(pctrl, cfg, _pin, bit);
+ arg = pctrl->data->read_oen(pctrl, cfg, _pin, bit);
if (!arg)
return -EINVAL;
break;
@@ -1228,7 +1230,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev,
case PIN_CONFIG_OUTPUT_ENABLE:
arg = pinconf_to_config_argument(_configs[i]);
- ret = rzg2l_write_oen(pctrl, cfg, _pin, bit, !!arg);
+ ret = pctrl->data->write_oen(pctrl, cfg, _pin, bit, !!arg);
if (ret)
return ret;
break;
@@ -2685,6 +2687,8 @@ static struct rzg2l_pinctrl_data r9a07g043_data = {
.set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode,
.pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .read_oen = &rzg2l_read_oen,
+ .write_oen = &rzg2l_write_oen,
};
static struct rzg2l_pinctrl_data r9a07g044_data = {
@@ -2699,6 +2703,8 @@ static struct rzg2l_pinctrl_data r9a07g044_data = {
.set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode,
.pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .read_oen = &rzg2l_read_oen,
+ .write_oen = &rzg2l_write_oen,
};
static struct rzg2l_pinctrl_data r9a08g045_data = {
@@ -2712,6 +2718,8 @@ static struct rzg2l_pinctrl_data r9a08g045_data = {
.set_pfc_mode = &rzg2l_pinctrl_set_pfc_mode,
.pm_set_pfc = &rzg2l_pinctrl_pm_setup_pfc,
.pmc_writeb = &rzg2l_pmc_writeb,
+ .read_oen = &rzg2l_read_oen,
+ .write_oen = &rzg2l_write_oen,
};
static const struct of_device_id rzg2l_pinctrl_of_table[] = {
--
2.34.1
