Hi Geert, On Wed, Mar 6, 2024 at 9:53 AM Geert Uytterhoeven <geert@xxxxxxxxxxxxxx> wrote: > > Hi Prabhakar, > > Thanks for your patch! > > On Tue, Mar 5, 2024 at 6:16 PM Prabhakar <prabhakar.csengg@xxxxxxxxx> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx> > > > > Document support for the Serial Communication Interface with FIFO (SCIF) > > available in the Renesas RZ/V2H(P) (R9A09G057) SoC. The SCIF interface in > > the Renesas RZ/V2H(P) is similar to that available in the RZ/G2L > > (R9A07G044) SoC, with the only difference being that the RZ/V2H(P) SoC has > > three additional interrupts: one for Tx end/Rx ready and the other two for > > Rx and Tx buffer full, which are edge-triggered. > > > > No driver changes are required as generic compatible string > > "renesas,scif-r9a07g044" will be used as a fallback on RZ/V2H(P) SoC. > > If you declare SCIF on RZ/V2H compatible with SCIF on RZ/G2L, you > state that the current driver works fine (but perhaps suboptimal), > without adding support for the extra 3 interrupts? > Yes the current driver works without using the extra interrupts on the RZ/V2H. The extra interrupts on the RZ/V2H are just sort of duplicate ie - Transmit End/Data Ready interrupt , for which we we have two seperate interrupts already - Receive buffer full interrupt (EDGE trigger), for which we already have a Level triggered interrupt - Transmit buffer empty interrupt (EDGE trigger), for which we already have a Level triggered interrupt Are you suggesting to not fallback on RZ/G2L and instead make RZ/V2H an explicit one so that in future we handle these 3 extra interrupts? Cheers, Prabhakar
