Hi Shimoda-san,
Thanks for your patch!
On Wed, Feb 14, 2024 at 6:21 AM Yoshihiro Shimoda
<yoshihiro.shimoda.uh@xxxxxxxxxxx> wrote:
> This SoC has GICv3 ITS and PCIe host mode on this SoC can use it.
> So, add GIC ITS node into GIC node and update interrupt-map in PCIe node.
>
> Note that PCIe nodes need msi-parent property to use the ITS for MSI.
> However, it requires PCIe driver's update. Especially, vendor-specific
> registers' setting is needed. So, this patch doesn't add msi-parent
> properties into PCIe nodes.
>
> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@xxxxxxxxxxx>
Is there any value in adding the GICv3 ITS node now, without msi-parent
properties pointing to it?
I.e. does applying this patch enable extra functionality yet?
> --- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
> @@ -1262,11 +1262,19 @@ ipmmu_mm: iommu@eefc0000 {
> gic: interrupt-controller@f1000000 {
> compatible = "arm,gic-v3";
> #interrupt-cells = <3>;
> - #address-cells = <0>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> interrupt-controller;
> reg = <0x0 0xf1000000 0 0x20000>,
> <0x0 0xf1060000 0 0x110000>;
> interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> +
> + gic_its: msi-controller@f1040000 {
> + compatible = "arm,gic-v3-its";
> + reg = <0x0 0xf1040000 0 0x20000>;
> + msi-controller;
Missing "#msi-cells = <1>", which is a required property.
> + };
> };
>
> prr: chipid@fff00044 {
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
