Hi Romain, On Mon, 12 Feb 2024 17:42:14 +0100 Romain Gantois <romain.gantois@xxxxxxxxxxx> wrote: > The GMAC1 controller in the RZN1 IP requires the RX MII clock signal to be > started before it initializes its own hardware, thus before it calls > phylink_start. > > Check the rxc_always_on pcs flag and enable the clock signal during the > link validation phase. It looks like this commit log doesn't match the content of the commit. > Reported-by: Clément Léger <clement.leger@xxxxxxxxxxx> > Link: https://lore.kernel.org/linux-arm-kernel/20230116103926.276869-4-clement.leger@xxxxxxxxxxx/ > Signed-off-by: Romain Gantois <romain.gantois@xxxxxxxxxxx> > --- > drivers/net/pcs/pcs-rzn1-miic.c | 27 +++++++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/drivers/net/pcs/pcs-rzn1-miic.c b/drivers/net/pcs/pcs-rzn1-miic.c > index d93f84fbb1fd..b0d9736c678e 100644 > --- a/drivers/net/pcs/pcs-rzn1-miic.c > +++ b/drivers/net/pcs/pcs-rzn1-miic.c > @@ -279,10 +279,37 @@ static int miic_validate(struct phylink_pcs *pcs, unsigned long *supported, > return -EINVAL; > } > > +static int miic_pre_init(struct phylink_pcs *pcs) > +{ > + struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs); > + struct miic *miic = miic_port->miic; > + u32 val; > + > + /* Start RX clock if required */ > + if (pcs->rxc_always_on) { > + /* In MII through mode, the clock signals will be driven by the > + * external PHY, which might not be initialized yet. Set RMII > + * as default mode to ensure that a reference clock signal is > + * generated. > + */ > + miic_port->interface = PHY_INTERFACE_MODE_RMII; There's this check in miic_config : if (interface != miic_port->interface) { val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed); mask |= MIIC_CONVCTRL_CONV_SPEED; miic_port->interface = interface; } As you set the interface to RMII and set the CONV_MODE below without really looking at the speed, is there any risk of a mismatch between the configured mode and the speed ? Thanks, Maxime
