This patch series aims to add HW checksum offload supported by TOE module
found on the RZ/G2L Gb ethernet IP.
TOE has hardware support for calculating IP header and TCP/UDP/ICMP
checksum for both IPv4 and IPv6.
For Rx, the 4-byte result of checksum calculation is attached to the
Ethernet frames.First 2-bytes is result of IPv4 header checksum and next
2-bytes is TCP/UDP/ICMP checksum.
If a frame does not have checksum error, 0x0000 is attached as checksum
calculation result. For unsupported frames 0xFFFF is attached as checksum
calculation result. In case of an IPv6 packet, IPv4 checksum is always set
to 0xFFFF.
For Tx, the result of checksum calculation is set to the checksum field of
each IPv4 Header/TCP/UDP/ICMP of ethernet frames. For the unsupported
frames, those fields are not changed. If a transmission frame is an UDPv4
frame and its checksum value in the UDP header field is 0x0000, TOE does
not calculate checksum for UDP part of this frame as it is optional
function as per standards.
Add Tx/Rx checksum offload supported by TOE for IPv4 and TCP/UDP protocols.
Results of iperf3 in Mbps
RZ/V2L:
TCP(Tx/Rx) results with checksum offload Enabled: {921,932}
TCP(Tx/Rx) results with checksum offload Disabled: {867,612}
UDP(Tx/Rx) results with checksum offload Enabled: {950,946}
UDP(Tx/Rx) results with checksum offload Disabled: {952,920}
RZ/G2L:
TCP(Tx/Rx) results with checksum offload Enabled: {920,936}
TCP(Tx/Rx) results with checksum offload Disabled: {871,626}
UDP(Tx/Rx) results with checksum offload Enabled: {953,950}
UDP(Tx/Rx) results with checksum offload Disabled: {954,920}
RZ/G2LC:
TCP(Tx/Rx) results with checksum offload Enabled: {927,936}
TCP(Tx/Rx) results with checksum offload Disabled: {889,626}
UDP(Tx/Rx) results with checksum offload Enabled: {950,946}
UDP(Tx/Rx) results with checksum offload Disabled: {949,944}
v4->v5:
* Updated comment related to TOE register in enum ravb_reg.
* Dropped CSR{1,2}_ALL from enum CSR{1,2}_BIT.
* Removed setting unnecessary bits in CSR{1,2}.
v3->v4:
* Add separate section for RZ/G2L TOE registers in enum ravb_reg.
* Dropped enabling IPv6 specific bits in CSR2.
* The comment "csum" expanded to "checksum" in ravb_rx_csum_gbeth().
* Dropped unnecessary comment "Hardware validated our checksum".
* Dropped reading CSR0 register in ravb_endisable_csum_gbeth().
* Restored NETIF_F_HW_CSUM and associated changes.
* Dropped enabling IPv6 specific bits in CSR1.
* Dropped enabling ICMPv4 specific bit and associated handling as linux
does not support it.
v2->v3:
* Updated commit header and description as suggested by Sergey for cover letter,
* patch#1 and patch#2.
* Dropped TOE_RX_CSUM_OK macro.
* Renamed ravb_csum_offload_init_gbeth()->ravb_csum_init_gbeth().
* Moved enabling {RPE,TPE} in ravb_csum_init_gbeth().
* Updated the error message in ravb_csum_init_gbeth() as
"Timeout enabling hardware checksum"
* Introduced ravb_endisable_csum_gbeth() for enabling/disabling CSR{1,2} registers.
* Replaced NETIF_F_IP_CSUM->NETIF_F_HW_CSUM as we are supporting only IPv4.
* Updated the comment related to UDP header field.
* Renamed ravb_is_tx_checksum_offload_gbeth_possible()->ravb_is_tx_csum_gbeth().
v1->v2:
* Updated covering letter and results
* Fixed the sparse warnings for patch#1 by replacing __sum16->__wsum.
Biju Das (2):
ravb: Add Rx checksum offload support for GbEth
ravb: Add Tx checksum offload support for GbEth
drivers/net/ethernet/renesas/ravb.h | 34 +++++-
drivers/net/ethernet/renesas/ravb_main.c | 149 ++++++++++++++++++++++-
2 files changed, 179 insertions(+), 4 deletions(-)
--
2.25.1
