On Thu, Feb 01, 2024 at 01:21:55PM +0100, Geert Uytterhoeven wrote: > From: Cong Dang <cong.dang.xn@xxxxxxxxxxx> > > Add the module clock used by the RCLK Watchdog Timer on the Renesas > R-Car V4M (R8A779H0) SoC. > > Signed-off-by: Cong Dang <cong.dang.xn@xxxxxxxxxxx> > Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx> Reviewed-by: Wolfram Sang <wsa+renesas@xxxxxxxxxxxxxxxxxxxx>
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