From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
Hi All,
The IAX45 block on RZ/Five SoC is almost identical to the IRQC bock found
on the RZ/G2L family of SoCs.
IAX45 performs various interrupt controls including synchronization for the
external interrupts of NMI, IRQ, and GPIOINT and the interrupts of the
built-in peripheral interrupts output by each module. And it notifies the
interrupt to the PLIC.
- Select 32 TINT from 82 GPIOINT.
- Integration of bus error interrupts from system bus.
- Integration of ECC error interrupts from On-chip RAM.
- Indicate interrupt status. (NMI, IRQ, TINT, integrated bus error interrupt
and integrated ECC error interrupt)
- Setting of interrupt detection method. (NMI, IRQ and TINT)
- All interrupts are masked by INTMASK.
- Mask function for NMI, IRQ and TINT
This patch series adds support for IAX45 in the IRQC driver and enables this
on RZ/Five SoC.
Cheers,
Prabhakar
Lad Prabhakar (5):
dt-bindings: interrupt-controller: renesas,rzg2l-irqc: Document
RZ/Five SoC
irqchip/renesas-rzg2l: Add support for RZ/Five SoC
riscv: dts: renesas: r9a07g043f: Add IRQC node to RZ/Five SoC DTSI
arm64: dts: renesas: r9a07g043: Move interrupt-parent property to
common DTSI
riscv: dts: renesas: rzfive-smarc-som: Drop deleting interrupt
properties from ETH0/1 nodes
.../renesas,rzg2l-irqc.yaml | 27 ++++
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 1 +
arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 4 -
arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 76 ++++++++++
.../boot/dts/renesas/rzfive-smarc-som.dtsi | 16 ---
drivers/irqchip/irq-renesas-rzg2l.c | 132 +++++++++++++++++-
6 files changed, 232 insertions(+), 24 deletions(-)
--
2.34.1
