Hi Geert,
Thanks for your work.
On 2024-01-26 11:50:56 +0100, Geert Uytterhoeven wrote:
> From: Cong Dang <cong.dang.xn@xxxxxxxxxxx>
>
> Add the module clocks used by the Pin Function Controller (PFC) and
> General Purpose Input/Output (GPIO) blocks on the Renesas R-Car V4M
> (R8A779H0) SoC.
>
> Signed-off-by: Cong Dang <cong.dang.xn@xxxxxxxxxxx>
> Signed-off-by: Geert Uytterhoeven <geert+renesas@xxxxxxxxx>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@xxxxxxxxxxxx>
> ---
> Changes compared to the BSP:
> - Change parent clock from CL16M to CP.
>
> To be queued in renesas-clk for v6.9.
> ---
> drivers/clk/renesas/r8a779h0-cpg-mssr.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/clk/renesas/r8a779h0-cpg-mssr.c b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> index 1259b8544980f07a..219941047291d34d 100644
> --- a/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779h0-cpg-mssr.c
> @@ -177,6 +177,9 @@ static const struct mssr_mod_clk r8a779h0_mod_clks[] = {
> DEF_MOD("hscif1", 515, R8A779H0_CLK_SASYNCPERD1),
> DEF_MOD("hscif2", 516, R8A779H0_CLK_SASYNCPERD1),
> DEF_MOD("hscif3", 517, R8A779H0_CLK_SASYNCPERD1),
> + DEF_MOD("pfc0", 915, R8A779H0_CLK_CP),
> + DEF_MOD("pfc1", 916, R8A779H0_CLK_CP),
> + DEF_MOD("pfc2", 917, R8A779H0_CLK_CP),
> };
>
> /*
> --
> 2.34.1
>
>
--
Kind Regards,
Niklas Söderlund
