Hi Prabhakar,
> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@xxxxxxxxx>
> Sent: Friday, January 12, 2024 2:26 PM
> Subject: [PATCH v4 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing
> port pins P19 to P28
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
>
> Add the missing port pins P19 to P28 for RZ/Five SoC. These additional
> pins provide expanded capabilities and are exclusive to the RZ/Five SoC.
>
> Couple of port pins have different configuration and are not identical for
> the complete port so introduce struct rzg2l_variable_pin_cfg to handle
> such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config
> is then assigned in rzg2l_pinctrl_get_variable_pin_cfg().
>
> Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO
> pins which support interrupt facility.
>
> While at define RZG2L_GPIO_PORT_PACK() using
> RZG2L_GPIO_PORT_SPARSE_PACK().
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@xxxxxxxxxxxxxx>
> ---
> drivers/pinctrl/renesas/pinctrl-rzg2l.c | 213 +++++++++++++++++++++++-
> 1 file changed, 204 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> index 8b8644d2c355..04bb21d564d4 100644
> --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c
> @@ -57,6 +57,8 @@
> #define PIN_CFG_IOLH_C BIT(13)
> #define PIN_CFG_SOFT_PS BIT(14)
> #define PIN_CFG_OEN BIT(15)
> +#define PIN_CFG_VARIABLE BIT(16)
> +#define PIN_CFG_NOGPIO_INT BIT(17)
>
> #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \
> (PIN_CFG_IOLH_##group | \
> @@ -76,17 +78,23 @@
> PIN_CFG_FILNUM | \
> PIN_CFG_FILCLKSEL)
>
> -/*
> - * n indicates number of pins in the port, a is the register index
> - * and f is pin configuration capabilities supported.
> - */
> #define PIN_CFG_PIN_MAP_MASK GENMASK(35, 28)
> #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20)
> #define PIN_CFG_MASK GENMASK(19, 0)
>
> -#define RZG2L_GPIO_PORT_PACK(n, a, f) ((((1ULL << (n)) - 1) << 28) | \
> - FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a))
> | \
> - FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
> +/*
> + * m indicates the bitmap of supported pins, a is the register index
> + * and f is pin configuration capabilities supported.
> + */
> +#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f)
> (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \
> +
> FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \
> + FIELD_PREP_CONST(PIN_CFG_MASK, (f)))
> +
> +/*
> + * n indicates number of pins in the port, a is the register index
> + * and f is pin configuration capabilities supported.
> + */
> +#define RZG2L_GPIO_PORT_PACK(n, a, f)
> RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f))
>
> /*
> * BIT(63) indicates dedicated pin, p is the register index while @@ -
> 200,6 +208,18 @@ struct rzg2l_dedicated_configs {
> u64 config;
> };
>
> +/**
> + * struct rzg2l_variable_pin_cfg - pin data cfg
> + * @cfg: port pin configuration
> + * @port: port number
> + * @pin: port pin
> + */
> +struct rzg2l_variable_pin_cfg {
> + u32 cfg:20;
> + u8 port:5;
u32 ??
> + u8 pin:5;
u32 ??
Cheers,
Biju
