Hi Mike, Stephen,
The following changes since commit 5f9e29b9159a41fcf6733c3b59fa46a90ce3ae20:
clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset() (2023-11-27 11:09:53 +0100)
are available in the Git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git tags/renesas-clk-for-v6.8-tag2
for you to fetch changes up to 515f05da372aedf347a1ac99d17fb832ba371d4d:
clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1 (2023-12-13 20:05:55 +0100)
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clk: renesas: Updates for v6.8 (take two)
- Add interrupt controller and Ethernet clocks and resets on RZ/G3S,
- Check reset monitor registers on RZ/G2L-alike SoCs.
Thanks for pulling!
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Claudiu Beznea (3):
clk: renesas: r9a08g045: Add IA55 pclk and its reset
clk: renesas: rzg2l: Check reset monitor registers
clk: renesas: r9a08g045: Add clock and reset support for ETH0 and ETH1
drivers/clk/renesas/r9a08g045-cpg.c | 13 ++++++++
drivers/clk/renesas/rzg2l-cpg.c | 59 +++++++++++++++++++++++++++----------
2 files changed, 57 insertions(+), 15 deletions(-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@xxxxxxxxxxxxxx
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
