On Wed, Dec 13, 2023 at 03:02:59PM +0800, Yu Chien Peter Lin wrote:
> xtheadpmu stands for T-Head Performance Monitor Unit extension.
> Based on the added T-Head PMU ISA string, the SBI PMU driver
> will make use of the non-standard irq source.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@xxxxxxxxxxxxx>
Acked-by: Conor Dooley <conor.dooley@xxxxxxxxxxxxx>
Cheers,
Conor.
> ---
> Changes v4 -> v5:
> - New patch
> ---
> arch/riscv/boot/dts/thead/th1520.dtsi | 8 ++++----
> 1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
> index ba4d2c673ac8..2dad2b22824a 100644
> --- a/arch/riscv/boot/dts/thead/th1520.dtsi
> +++ b/arch/riscv/boot/dts/thead/th1520.dtsi
> @@ -22,7 +22,7 @@ c910_0: cpu@0 {
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> + "zifencei", "zihpm", "xtheadpmu";
> reg = <0>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> @@ -46,7 +46,7 @@ c910_1: cpu@1 {
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> + "zifencei", "zihpm", "xtheadpmu";
> reg = <1>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> @@ -70,7 +70,7 @@ c910_2: cpu@2 {
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> + "zifencei", "zihpm", "xtheadpmu";
> reg = <2>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> @@ -94,7 +94,7 @@ c910_3: cpu@3 {
> riscv,isa = "rv64imafdc";
> riscv,isa-base = "rv64i";
> riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> - "zifencei", "zihpm";
> + "zifencei", "zihpm", "xtheadpmu";
> reg = <3>;
> i-cache-block-size = <64>;
> i-cache-size = <65536>;
> --
> 2.34.1
>
Attachment:
signature.asc
Description: PGP signature
