Hi Uwe Kleine-König, > -----Original Message----- > From: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> > Sent: Friday, December 8, 2023 2:07 PM > Subject: Re: [PATCH v17 3/4] pwm: Add support for RZ/G2L GPT > > Hello Biju, > > On Fri, Dec 08, 2023 at 10:34:55AM +0000, Biju Das wrote: > > > -----Original Message----- > > > From: Uwe Kleine-König <u.kleine-koenig@xxxxxxxxxxxxxx> > > > Sent: Thursday, December 7, 2023 9:42 PM > > > Subject: Re: [PATCH v17 3/4] pwm: Add support for RZ/G2L GPT > > > > > > Hello Biju, > > > > > > On Thu, Dec 07, 2023 at 06:26:44PM +0000, Biju Das wrote: > > > > ######[ 304.213944] pwm-rzg2l-gpt 10048000.pwm: .apply is not > > > > idempotent (ena=1 pol=0 5500000000000/43980352512000) -> (ena=1 > > > > pol=0 > > > > 5500000000000/43980239923200) > > > > High setting## > > > > [ 304.230854] pwm-rzg2l-gpt 10048000.pwm: .apply is not > > > > idempotent > > > > (ena=1 pol=0 23980465100800/43980352512000) -> (ena=1 pol=0 > > > > 23980465100800/43980239923200) > > > > > > Have you tried to understand that? What is the clk rate when this > happens? > > > You're not suggesting that mul_u64_u64_div_u64 is wrong, are you? > > > > mul_u64_u64_div_u64() works for certain values. But for very high > > values we are losing precision and is giving unexpected values. > > Can you reduce the problem to a bogus result of mul_u64_u64_div_u64()? > I'd be very surprised if the problem was mul_u64_u64_div_u64() and not how > it's used in your pwm driver. When I looked last time, it drops precision here[1]. I will recheck again. On RZ/G2L family devices, the PWM rate is 100MHz. [1] https://elixir.bootlin.com/linux/v6.7-rc4/source/lib/math/div64.c#L214 Cheers, Biju
